With the rapid growth of the semiconductor industry, high-density semiconductor memory devices have already reached the gigabit scale, led by the progressive development of dynamic random access memory (DRAM) technology. Meanwhile, the increasing speed gap between the logic and DRAM technologies has led to complex memory hierarchies and the need for high speed on-chip DRAMS.
One common DRAM memory cell involves a single access transistor and a capacitor in a one-transistor, one-capacitor (1T1C) arrangement, where information is stored in the form of charge on the capacitor. Although the DRAM cell has generally exhibited a smaller cell size relative to other cells, ranging between 4F2 and 8F2, where F is the minimum feature size, it requires periodic refreshing because of the leakage of charge on the capacitor. As technology scales, the transistor leakage current keeps increasing, which only exacerbates the data retention problem. In this regard, the threshold voltage of the access transistor is generally kept at a high level, since reducing the threshold voltage results in an exponential increase in subthreshold leakage and, therefore, much smaller data retention time. With these challenges, the continued scaling of DRAM technology to much higher densities and higher performances presents significant technological challenges.
Static RAM (SRAM) does not require refreshing and is generally faster than DRAM (e.g., approaching a nanosecond or shorter for access time, relative to tens of nanoseconds for access to DRAM cells). However, SRAM cells have generally been significantly more complex than DRAM cells, and in some applications requiring either four n-channel MOSFETs and two p-channel MOSFETs, or four n-channel MOSFETs and two polysilicon load resistors. These complex SRAM arrangements have generally resulted in significantly larger cell size (typically greater than 100F2), relative to DRAM cell sizes.
Negative differential resistance (NDR) devices have been proposed for compact static memory applications, where NDR devices are added to a 1T1C DRAM cell. Generally, if the current of the NDR element can compensate for the leakage of the memory cell, the information stored in the capacitor will not be lost and therefore a static high-density memory cell can be achieved. However, most SRAM applications involving NDR devices have suffered from a variety of undesirable operational characteristics. In addition, the manufacture of such devices has often required processes that are not readily implemented with common CMOS-type fabrication, require additional steps and/or cost.
These and other characteristics have been challenging to the implementation of negative differential resistance devices in memory and various other applications.